library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity spislave is
generic( N: integer := 8);
port
( sclk    : in std_logic;
  cs      : in std_logic;
  data_Tx : in std_logic_vector(N-1 downto 0); 
  data_Rx : out std_logic_vector(N-1 downto 0);
  miso    : out std_logic; 
  mosi    : in std_logic; 
  reset   : in std_logic  ); 
end entity spislave;
architecture rtl of spislave is
  signal i: integer range 0 to N-1; 
  signal j: integer range 0 to N-1; 
  signal tempdata : std_logic_vector(N-1 downto 0);
   
begin

process (sclk,reset,cs,mosi) 
  begin
  if reset='0' then 
    tempdata<= "00000000";
    i<=N-1;
  elsif (rising_edge(sclk)) then 
      i <= i-1;
      tempdata<=tempdata(N-2 downto 0)&mosi;      
  end if; 
  end process;
 process(sclk,cs,i)
  begin
  if reset='0' or cs='1' then
     miso<=data_Tx(i);
  elsif (falling_edge(sclk)) then
     miso<=data_Tx(i);
  end if;
  end process;

  process(reset,cs)
  begin
   if reset='0' then
     data_Rx<=x"00";
   elsif cs='1' then
     data_Rx<=tempdata;
   end if;
  end process;
  end rtl;