library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity spimain is
generic( N: integer := 8);
port
( fclk    : in std_logic;
  sclk    : out std_logic;
  cs      : out std_logic;
  data_Tx : in std_logic_vector(N-1 downto 0); 
  data_Rx : out std_logic_vector(N-1 downto 0);
  miso    : in std_logic;
  mosi    : out std_logic;
  reset   : in std_logic  );
end entity spimain;
architecture rtl of spimain is
  type s    is (s0,s1,s2,s3);
  signal    state           : s;
  signal i: integer range 0 to N-1;
  signal tempdata : std_logic_vector(N-1 downto 0);
--  signal j: std_logic; 
--  signal buff: std_logic_vector(N-1 downto 0);

begin


process (fclk,reset)
  begin
  if reset='0' then
    tempdata<= "00000000";
    sclk<='0';
    mosi<='0';
    cs<='1';
--    j <= '1';
    i<=N-1;
    state<=s0;
  elsif (rising_edge(fclk)) then
    case state is
     when s0=>
       data_Rx<=tempdata;
       cs<='0';
       sclk<='0';
       mosi<=data_Tx(i);
      -- i<=N-1;
       state<=s1;
     when s1=>
       sclk<='1';
       tempdata<=tempdata(N-2 downto 0)&miso;
       i<=i-1;
       state<=s2;
     when s2=>
       sclk<='0';
       mosi<=data_Tx(i);
       if i=0 then
       state<=s3;
       else
       state<=s1;
       end if;
      when s3=>
       sclk<='1';
       i<=N-1;
       tempdata<=tempdata(N-2 downto 0)&miso;
       state<=s0;
      when others=>
       state<=s0;
      end case;
    end if ;
   end process;
   end rtl;