module	five(
output			clk_g,

input			clk,
input			rst_n);

reg		[1:0]			cnt_1;
reg						clk_g_1;
always@(posedge clk,negedge rst_n)
	if(!rst_n)
		cnt_1 <= 2'd0;
	else if(cnt_1 == 2)
		cnt_1 <= 2'd0;
	else
		cnt_1 <= cnt_1 + 1'b1;
		
always@(posedge clk,negedge rst_n)
	if(!rst_n)
		clk_g_1 <= 1'b0;
	else if(cnt_1 == 1)
		clk_g_1 <= ~clk_g_1;
	else if(cnt_1 == 2)
		clk_g_1 <= ~clk_g_1;
		
reg		[1:0]			cnt_2;
reg						clk_g_2;
always@(negedge clk,negedge rst_n)
	if(!rst_n)
		cnt_2 <= 2'd0;
	else if(cnt == 2)
		cnt_2 <= 2'd0;
	else
		cnt_2 <= cnt_2 + 1'b1;
		
always@(negedge clk,negedge rst_n)
	if(!rst_n)
		clk_g_2 <= 1'b0;
	else if(cnt_2 == 1)
		clk_g_2 <= ~clk_g_2;
	else if(cnt_2 == 2)
		clk_g_2 <= ~clk_g_2;
		
assign clk_g = clk_g_1 | clk_g_2;
		
endmodule