//**************
//EMIFA of TI
//

module EMIFA_V1_my(

		ema_clk, ema_rst,
		
		dsl_a,
		dsl_di,
		dsl_do,
		dsl_be_l,
		dsl_ba,
		dsl_oe_l,
		dsl_ce_l,
		dsl_we_l,
		dsl_wait

);

output		[5:0]		dsl_a;
input			[15:0]	dsl_di;
output		[15:0]	dsl_do;
output					dsl_be_l;
output					dsl_ba;
output					dsl_oe_l;
output					dsl_ce_l;
output					dsl_we_l;
input						dsl_wait;

reg			[5:0]		dsl_a;
reg			[15:0]	dsl_do;
reg						dsl_be_l;
reg						dsl_ba;
reg						dsl_oe_l;
reg						dsl_ce_l;
reg						dsl_we_l;

parameter	[6:0]		IdleState		= 7'b0000001;
parameter	[6:0]		WrSetupState	= 7'b0000010;
parameter	[6:0]		WrStrobeState	= 7'b0000100;
parameter	[6:0]		WrHoldState		= 7'b0001000;
parameter	[6:0]		RdSetupState	= 7'b0010000;
parameter	[6:0]		RdStrobeState	= 7'b0100000;
parameter	[6:0]		RdHoldState		= 7'b1000000;

// main finite state machine
reg		[3:0]		EMIFA_STATE;
wire					wr_en;
wire					rd_en;
always @( posedge ema_clk or posedge ema_rst )
begin
	if(ema_rst)
	begin
		EMIFA_STATE		<= IdleState;
	end
	else
	begin
		case( EMIFA_STATE )
		IdleState:
		begin
			if( wr_en )
				EMIFA_STATE		<= WrSetupState;
			else if( rd_en )
				EMIFA_STATE		<= RdSetupState;
			else 
				EMIFA_STATE		<= IdleState;
		end
		//--------Write---
		WrSetupState:
		begin
			if( wait_cnt == 1 )
				EMIFA_STATE		<= WrStrobeState;
		end
		WrStrobeState:
		begin
			if( wait_cnt == 8 )
				EMIFA_STATE		<= WrHoldState;
		end
		WrHoldState:
		begin
			if( wait_cnt == 9 )
				EMIFA_STATE		<= IdleState;
		end
		//-------Read----
		RdSetupState:
		begin
			if( wait_cnt == 1 )
				EMIFA_STATE		<= RdStrobeState;
		end
		RdStrobeState:
		begin
			if( wait_cnt == 8 )
				EMIFA_STATE		<= RdHoldState;
		end
		RdHoldState:
		begin
			if( wait_cnt == 9 )
				EMIFA_STATE		<= IdleState;
		end
		default:	EMIFA_STATE		<= IdleState;
		endcase
	end
end

reg		[3:0]		wait_cnt;
always @( posedge ema_clk or posedge ema_rst )
begin
	if(ema_rst)
	begin
		wait_cnt		<= 4'b0;
	end
	else if( wr_en | rd_en )
	begin
		wait_cnt		<= 4'b0;
	end
	else if( wait_cnt < 12 )
	begin
		wait_cnt		<= wait_cnt + 1'b1;
	end
end

// state output
reg		[15:0]	rd_data;
reg					wr_done;
reg					rd_done;
always @( * )
begin
	if(ema_rst)
	begin
		dsl_ce_l		= 1'b1;
		dsl_we_l		= 1'b1;
		dsl_oe_l		= 1'b1;
		dsl_a			= 6'b0;
		dsl_do		= 16'b0;
	end
	else
	begin
		case( EMIFA_STATE )
		IdleState:
		begin
			dsl_ce_l		= 1'b1;
			dsl_we_l		= 1'b1;
			dsl_oe_l		= 1'b1;
			dsl_a			= 6'b0;
			dsl_do		= 16'b0;
			wr_done		= 1'b0;
			rd_done		= 1'b0;
		end
		//--------Write---
		WrSetupState:
		begin
			dsl_a			= wr_addr;
			dsl_do		= wr_data;
		end
		WrStrobeState:
		begin
			dsl_ce_l		= 1'b0;
			dsl_we_l		= 1'b0;
		end
		WrHoldState:
		begin
			dsl_ce_l		= 1'b1;
			dsl_we_l		= 1'b1;
			wr_done		= 1'b1;
		end
		//-------Read----
		RdSetupState:
		begin
			dsl_a			= rd_addr;
		end
		RdStrobeState:
		begin
			dsl_ce_l		= 1'b0;
			dsl_oe_l		= 1'b0;
		end
		RdHoldState:
		begin
			dsl_ce_l		= 1'b1;
			dsl_oe_l		= 1'b1;
			rd_data		= dsl_di;
			rd_done		= 1'b1;
		end
		default:	dsl_ce_l		= 1'b1;;
		endcase
	end
end

assign	dsl_ba	= 1'b0;
assign	dsl_be_l = 2'b00;

endmodule